The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). An MOS transistor includes a gate electrode as a control electrode that is formed overlying a semiconductor substrate and spaced-apart source and drain regions that are formed within the semiconductor substrate and between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel in the semiconductor substrate between the source and drain regions and beneath the gate electrode.
The MOS transistor is accessed via a conductive contact typically formed on the source/drain regions between the gate electrodes of two MOS transistors. The conductive contact is usually formed by depositing an insulating layer over the source/drain regions and etching a contact opening in the insulating layer. A thin barrier layer, typically of titanium nitride and/or other metals and alloys, is deposited in the contact opening and the opening then is filled by a chemical vapor deposited layer of tungsten.
There is a continuing trend to incorporate more and more circuitry on a single IC chip. To incorporate the increasing amount of circuitry, the size of each individual device in the circuit and the size and spacing between device elements must decrease. However, one of the limiting factors in the continued shrinking of integrated semiconductor devices is the resistance of contacts to doped regions such as the source and drain regions of an MOS transistor. As device sizes decrease, the width of the contact decreases. As the width of the contact decreases, the resistance of the contact becomes increasingly larger. In turn, as the resistance of the contact increases, the drive current of the device decreases, thus adversely affecting device performance.
Accordingly, it is desirable to provide MOS structures that exhibit lower contact resistance. In addition, it is desirable to provide methods for fabricating MOS structures that exhibit lower contact resistance. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.